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Micrel, Inc.
7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
SY58011U Precision Edge(R) SY58011U
FEATURES
Precision 1:2, 400mV CML fanout buffer Guaranteed AC performance over temperature/ voltage: * > 7GHz fMAX clock * < 60ps tr / tf times * < 250ps tpd * < 15ps max. skew Low jitter performance: * < 10psPP total jitter (clock) * < 1psRMS random jitter (data) * < 10psPP deterministic jitter (data) Accepts an input signal as low as 100mV Unique input termination and VT pin accepts DCcoupled and AC-coupled differential inputs: LVPECL, LVDS, and CML 50 source terminated CML outputs Power supply 2.5V 5% and 3.3V 10% Industrial temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) MLF(R) package Precision Edge(R)
DESCRIPTION
The SY58011U is a 2.5V/3.3V precision, high-speed, fully differential 1:2 CML fanout buffer. Optimized to provide two identical output copies with less than 15ps of skew and less than 10ps(pk-pk) total jitter, the SY58011U can process clock signals as fast as 7GHz or data patterns up to 10.7Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS, or CML differential signals, (AC-coupled or DC-coupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference voltage (VREF-AC) is provided to bias the VT pin. The outputs are compatible with 400mV typical swing into 50 loads, with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58011U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require LVPECL outputs, consider the SY58012U or SY58013U 1:2 fanout buffer with 800mV and 400mV output swing, respectively. The SY58011U is part of Micrel's highspeed, Precision Edge(R) product line. Datasheets and support documentation can be found on Micrel's web site at www.micrel.com.
APPLICATIONS
s s s s s All SONET and GigE clock distribution Fibre Channel clock and data distribution Backplanes Data distribution: OC-48, OC-48+FEC, XAUI High-end, low skew, multiprocessor synchronous clock distribution
TYPICAL PERFORMANCE
2GHz Output
FUNCTIONAL BLOCK DIAGRAM
Output Swing (100mV/div.)
VCC = 2.5V
IN 50 VT 50 /IN VREF-AC
Q0 /Q0
Q1 /Q1
TIME (70ps/div.)
2GHz with 100mV Input
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-051408 hbwhelp@micrel.com or (408) 955-1690
Rev.: F Amendment: /0
1
Issue Date: May 2008
Micrel, Inc.
SY58011U
PACKAGE/ORDERING INFORMATION
GND GND VCC VCC
Ordering Information(1)
Part Number
12 11 10 9
16
15
14
13
Package Type MLF-16 MLF-16 MLF-16 MLF-16
Operating Range Industrial Industrial Industrial Industrial
Package Marking 011U 011U 011U with Pb-Free bar-line indicator 011U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
IN VT VREF-AC /IN
1 2 3 4 5 6 7 8
Q0 /Q0 /Q1 Q1
SY58011UMI SY58011UMITR(2) SY58011UMG(3) SY58011UMGTR(2, 3)
GND
VCC
GND
VCC
16-Pin MLF(R) (MLF-16)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number 1, 4 Pin Name IN, /IN Pin Function Differential Input: This input pair is the signal to be buffered. Each pin of this pair internally terminates with 50 to the VT pin. Note that this input will default to an indeterminate state if left open. See "Input Interface Applications" section. Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See "Input Interface Applications" section. Reference Output Voltage: This output biases to VCC -1.2V. It is used when AC-coupling the inputs (IN, /IN). Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. Maximum current source or sink is 0.5mA. See "Input Interface Applica tions" section. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins as possible. Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. CML Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 400mV. Unused output pairs may be left floating with no impact on jitter. See "CML Output Termination" section.
2
VT
3
VREF-AC
5, 8, 13, 16 6, 7, 14, 15 12, 11 9, 10
VCC GND, (Exposed Pad) Q0, /Q0, Q1, /Q1
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Micrel, Inc.
SY58011U
Absolute Maximum Ratings(Note 1)
Power Supply Voltage (VCC) ....................... -0.5V to +4.0V Input Voltage (VIN) ......................................... -0.5V to VCC CML Output Voltage (VOUT) ........... VCC-1.0V to VCC+0.5V Current (VT) Source or sink current on VT pin ........................ 100mA Input Current Source or sink current on IN, /IN .......................... 50mA Current (VREF) Source or sink current on VREF-AC, Note 4 ........ 1.5mA Lead Temperature Soldering, (20 seconds) .............. 260C Storage Temperature Range (TSTORE) .... -65C to +150C
Operating Ratings(Note 2)
Supply Voltage (VCC) ............................ +2.375V to +3.60V Operating Temperature Range (TA) ........... -40C to +85C Package Thermal Resistance, Note 3 MLF(R) (JA) Still-Air ............................................................. 60C/W 500lfpm ............................................................ 54C/W MLF(R) (JB) .......................................................... 33C/W
DC ELECTRICAL CHARACTERISTICS(Note 5)
TA= -40C to +85C Symbol VCC ICC VIH VIL VIN VDIFF_IN RIN VREF-AC IN to VT Parameter Power Supply Voltage Power Supply Current Input HIGH Voltage Input LOW Voltage Input Voltage Swing Differential Input Voltage Swing Into VT Resistance Output Reference Voltage Max. VCC, no load IN, /IN, Note 6 IN, /IN see Figure 1a. see Figure 1b. VCC-1.6 0 0.1 0.2 40 VCC -1.3 50 VCC -1.2 60 VCC -1.1 1.28 Condition Min 2.375 75 Typ Max 3.60 95 VCC VIH-0.1 1.7 Units V mA V V V V V V
CML DC ELECTRICAL CHARACTERISTICS(Note 5)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C; RL = 100 across each output pair, or equivalent, unless otherwise stated. Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output HIGH Voltage Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Condition Q0, /Q0, Q1, /Q1 Q0, /Q0, Q1, /Q1; see Figure 1a. Q0, /Q0, Q1, /Q1; see Figure 1b. Q0, /Q0, Q1, /Q1 Min Typ Max VCC Units V mV mV 60 VCC -0.020 VCC -0.010 325 650 40 400 800 50
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (gnd) on the pcb. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. 6. VIH (min) not lower than 1.2V.
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Micrel, Inc.
SY58011U
AC ELECTRICAL CHARACTERISTICS (Note 7)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to +85C; RL = 100 across each output pair, or equivalent, unless otherwise stated. Symbol fMAX tpd tCHAN tSKEW tJITTER Parameter Maximum Operating Frequency VOUT 200mV Propagation Delay Channel-to-Channel Skew Part-to-Part Skew Data Clock tr, tf
Notes: 7. 8. 9. High frequency AC electricals are guaranteed by design and characterization. Skew is measured between outputs of the same bank under identical transitions. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
Condition NRZ Data Clock
Min
Typ 10.7
Max
Units Gbps GHz
7 100
8 170 3 250 15 100 1 10 1 10
VIN 100mV Note 8 Note 9 Note 10 Note 11 Note 12 Note 13 20% to 80% at full output swing
ps ps ps psRMS psPP psRMS psPP ps
Random Jitter (RJ) Deterministic Jitter (DJ) Cycle-to-Cycle Jitter Total Jitter (TJ)
Output Rise/Fall Time
20
40
60
10. RJ is measured with a K28.7 comma detect character pattern, measured at 10.7Gbps and 2.5Gbps/3.2Gbps. 11. DJ is measured at 10.7Gbps and 2.5Gbps/3.2Gbps with both K28.5 and 223-1 PRBS pattern 12. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal. 13. Total jitter definition: With an ideal clock input of frequency fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value.
TIMING DIAGRAM
/IN IN
/Q Q tpd
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VIN, VOUT (Typ. 400mV)
VDIFF_IN, VDIFF_OUT (Typ. 800mV)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
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Micrel, Inc.
SY58011U
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, GND = 0, VIN = 100mV, TA = 25C, unless otherwise stated.
Frequency vs. Amplitude
WITHIN-DEVICE SKEW (ps)
10000
500 450
AMPLITUDE (mV)
10 9 8 7 6 5 4 3 2
Within-Device Skew vs. Temperature
400 350 300 250 200 150 100 50
12000 0 2000 4000 6000 8000
0
1 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
FREQUENCY (MHz)
162
Propagation Delay vs. Input Voltage Swing
PROPAGATION DELAY (ps)
160 158 156 154 152 150 0 200 400 600 800 1000 INPUT VOLTAGE SWING (V)
185 180 VIN 200mV 175 170 165 160 155 150 145 140 135 130 125 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
Propagation Delay vs. Temperature
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PROPAGATION DELAY (ps)
5
Micrel, Inc.
SY58011U
FUNCTIONAL CHARACTERISTICS
VCC = 2.5V, GND = 0, VIN = 100mV, TA = 25C, unless otherwise stated.
200MHz Output
2GHz Output
VCC = 2.5V
Output Swing (100mV/div.) Output Swing (100mV/div.)
TIME (600ps/div.)
TIME (70ps/div.)
7GHz Output
Output Swing (100mV/div.)
TIME (20ps/div.)
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Micrel, Inc.
SY58011U
INPUT STAGE
VCC
IN 509 VT 509 /IN GND
Figure 2. Simplified Differential Input Buffer
INPUT INTERFACE APPLICATIONS
VCC
VCC VCC
VCC IN
VCC
VCC
LVPECL
IN
/IN SY58011U
IN CML /IN SY58011U
CML /IN
5;#&7
VT
0.01F Rpd VCC NC
VT VREF-AC
NC NC
VT
VREF-AC
VREF-AC
0.01mF
VCC
Note: For VCC = 2.5V systems, Rpd = 19. For VCC = 3.3V systems, Rpd = 50.
Figure 3a. DC-Coupled CML Input Interface
(option: may connect VT to VCC)
VCC VCC
Figure 3b. AC-Coupled CML Input Interface
Figure 3c. LVPECL Input Interface
IN
LVPECL
VCC
VCC
/IN
Rpd
Rpd VT
5;#&7
IN LVDS /IN
VREF-AC 0.01mF Note: VCC
5;#&7
NC NC VT VREF-AC
Rpd = 100W for a 3.3V system Rpd = 50W for a 2.5V system
Figure 3d. AC-Coupled LVPECL Input Interface
Figure 3e. LVDS Input Interface
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Micrel, Inc.
SY58011U
CML OUTPUT TERMINATION
Figure 4 and Figure 5 illustrates how to terminate a CML output using both the AC-coupled and DC-coupled
VCC
configuration. All outputs of the SY58011 are 50 with a 16mA current source.
VCC 509
1009 /Q ZO 509
509
509
Q
ZO
=
509
509 Q 509 /Q 509 DC-bias per application
=
16mA
16mA GND
GND
Figure 4. CML DC-Coupled Termination
Figure 5. CML AC-Coupled Termination
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number SY58011U SY58012U SY58013U Function 7GHz, 1:2 CML Fanout Buffer/Translator with Internal I/O Termination 5GHz, 1:2 LVPECL Fanout Buffer/Translator with Internal Input Termination 6GHz, 1:2 Fanout Buffer/Translator with 400mV LVPECL Outputs and Internal Input Termination 16-MLF(R) Manufacturing Guidelines Exposed Pad Application Note HBW Solutions Data Sheet Link http://www.micrel.com/product-info/products/sy58011u.shtml http://www.micrel.com/product-info/products/sy58012u.shtml http://www.micrel.com/product-info/products/sy58013u.shtml www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf http://www.micrel.com/product-info/as/solutions.shtml
M9999-051408 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
SY58011U
16-PIN MicroLeadFrame(R) (MLF-16)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-051408 hbwhelp@micrel.com or (408) 955-1690
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